| CPC G09G 5/008 (2013.01) [G09G 2310/0291 (2013.01); G09G 2330/021 (2013.01)] | 20 Claims |
|
1. An electronic device comprising:
a host processor including a data transmitter;
a driving driver connected to the host processor in an interface mode and which receives data from the host processor; and
a display panel which is controlled by the driving driver, and
wherein the data transmitter includes:
a phase locked loop which generates a first clock and a second clock;
a clock block which receives the first clock and outputs a clock signal to a clock lane;
a plurality of data blocks which receives the second clock and respectively outputs serial data to a plurality of data lanes;
a first buffer connected between the phase locked loop and the clock block; and
a plurality of second buffers respectively connected between the phase locked loop and the plurality of data blocks,
wherein the first buffer is activated or deactivated depending on the interface mode to allow the clock block to receive or not to receive the first clock, and
wherein each of the plurality of second buffers is activated or deactivated depending on the interface mode to allow each of the plurality of data blocks to receive or not to receive the second clock.
|