US 12,190,842 B2
Semiconductor device, display module, and electronic device
Atsushi Umezaki, Kanagawa (JP)
Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Dec. 16, 2022, as Appl. No. 18/083,282.
Application 16/263,153 is a division of application No. 14/680,520, filed on Apr. 7, 2015, granted, now 10,199,006, issued on Feb. 5, 2019.
Application 18/083,282 is a continuation of application No. 17/029,099, filed on Sep. 23, 2020, abandoned.
Application 17/029,099 is a continuation of application No. 16/263,153, filed on Jan. 31, 2019, granted, now 10,839,766, issued on Nov. 17, 2020.
Claims priority of application No. 2014-090314 (JP), filed on Apr. 24, 2014.
Prior Publication US 2023/0162697 A1, May 25, 2023
Int. Cl. G09G 3/36 (2006.01); G09G 3/20 (2006.01); G11C 19/28 (2006.01); H03K 3/356 (2006.01); H03K 5/15 (2006.01); H03K 4/02 (2006.01)
CPC G09G 3/3674 (2013.01) [G09G 3/20 (2013.01); G09G 3/3688 (2013.01); G11C 19/28 (2013.01); H03K 3/356026 (2013.01); H03K 5/15066 (2013.01); H03K 5/15093 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0283 (2013.01); G09G 2310/0286 (2013.01); G11C 19/287 (2013.01); H03K 4/026 (2013.01)] 1 Claim
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal,
wherein one of a source and a drain of the second transistor is electrically connected to the output terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to a first power supply line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a second power supply line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a first signal line,
wherein a gate of the sixth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the fourth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the fifth transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to a second signal line,
wherein a gate of the eighth transistor is electrically connected to the other of the source and the drain of the eighth transistor,
wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the fifth transistor,
wherein a gate of the ninth transistor is electrically connected to a gate of the seventh transistor,
wherein the fourth transistor is configured to control a potential of the gate of the first transistor,
wherein the fifth transistor is configured to control a potential of the gate of the first transistor,
wherein the seventh transistor is configured to control a potential of the gate of the fourth transistor, and
wherein the ninth transistor is configured to control a potential of the gate of the fifth transistor.