CPC G09G 3/3648 (2013.01) [G02F 1/1309 (2013.01); G02F 1/134336 (2013.01); G02F 1/136286 (2013.01); H01L 27/124 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0439 (2013.01); G09G 2300/0852 (2013.01); G09G 2320/0209 (2013.01); G09G 2320/0233 (2013.01)] | 9 Claims |
1. A display panel comprising:
a base substrate; and
a pixel structure disposed on the base substrate, wherein the pixel structure comprises:
a first pixel electrode comprising a first main pixel area and a first sub-pixel area, wherein the first main pixel area and the first sub-pixel area are arranged in a second direction perpendicular to the first direction;
a second pixel electrode arranged in alternation with the first pixel electrode in a first direction and comprising a second main pixel area and a second sub-pixel area, wherein the second main pixel area and the second sub-pixel area are arranged in the second direction;
a transverse signal line located between the first main pixel area and the first sub-pixel area and extending in the first direction, wherein the transverse signal line is a scan signal line;
a first longitudinal signal line comprising a first main line and a first secondary-line extending along the second direction, wherein the first longitudinal signal line is a data signal line; and
a second longitudinal signal line comprising a second main line and a second secondary-line extending along the second direction, wherein the second longitudinal signal line is a data signal line;
wherein each of the first main line and the second main line is arranged in the first main pixel area, each of the first secondary-line and the second secondary-line is arranged in the first sub-pixel area, and electrical signals on the first longitudinal signal line and the second longitudinal signal line are opposite; and
wherein the display panel further comprises:
a first common electrode disposed on the base substrate;
a second common electrode disposed on the base substrate and in a same layer as the first common electrode;
a first insulating layer disposed on the base substrate and covering the first common electrode and the second common electrode; wherein the first longitudinal signal line and the second longitudinal signal line are disposed on the first insulating layer and in a same layer;
a second insulating layer disposed on the first insulating layer and covering the first longitudinal signal line and the second longitudinal signal line;
a first shared electrode disposed on the second insulating layer, wherein the first shared electrode is disposed between the first longitudinal signal line and the second longitudinal signal line in a direction parallel to the base substrate;
a second shared electrode disposed on the second insulating layer; and
a third insulating layer disposed on the second insulating layer and covering the first shared electrode and the second shared electrode;
wherein the first pixel electrode and the second pixel electrode are disposed on the third insulating layer, the first pixel electrode covers the first shared electrode, and the second pixel electrode covers the second shared electrode.
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