CPC G09G 3/3266 (2013.01) [G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01)] | 25 Claims |
1. A gate driving circuit comprising a plurality of stages, wherein each of the plurality of stages comprises:
a signal transmission unit connected between an input terminal to which a start signal is configured to be applied and a first node, and configured to transmit, to the first node, the start signal according to a clock signal;
a first inverter configured to control a voltage level of a second node according to a voltage level of the first node; and
a second inverter configured to output an output signal of a first voltage of a first voltage level or a second voltage of a second voltage level according to the voltage level of the second node,
wherein the second inverter comprises:
a first pull-up transistor connected between a first voltage input terminal and an output terminal, and comprising a gate connected to the second node, the first voltage input terminal configured to supply the first voltage;
a first pull-down transistor connected between a second voltage input terminal and the output terminal, and comprising a first gate connected to the second node and a second gate connected to a first control node, the second voltage input terminal configured to supply the second voltage;
a first capacitor connected between the first gate of the first pull-down transistor and the first control node; and
a first control transistor connected between the first control node and a ground terminal and comprising a gate connected to the ground terminal.
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