US 12,190,810 B2
Pixel circuit, display device, and driving method
Naobumi Toyomura, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 18/255,585
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Nov. 26, 2021, PCT No. PCT/JP2021/043419
§ 371(c)(1), (2) Date Jun. 1, 2023,
PCT Pub. No. WO2022/124099, PCT Pub. Date Jun. 16, 2022.
Claims priority of application No. 2020-204327 (JP), filed on Dec. 9, 2020.
Prior Publication US 2024/0112631 A1, Apr. 4, 2024
Int. Cl. G09G 3/3233 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/045 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A pixel circuit, comprising:
a first transistor configured to supply, in a light emission period of a first frame of a video signal, a current to a light emitting element based on a first voltage at a specific terminal of the first transistor;
a first capacitor configured to hold the first voltage;
a second transistor configured to sample, in the light emission period, a signal voltage of a video signal line,
wherein the signal voltage corresponds to a second frame of the video signal;
a second capacitor configured to hold the sampled signal voltage in the light emission period; and
a third transistor configured to:
connect the second capacitor to the first capacitor in the second frame and the light emission period; and
set, to the first capacitor, a second voltage corresponding to the signal voltage by transfer of electric charges accumulated in the second capacitor to the first capacitor,
wherein the electric charges are accumulated in the second capacitor in the light emission period.