US 12,190,803 B2
Array substrate and display apparatus
Tinghua Shang, Beijing (CN); Biao Liu, Beijing (CN); Siyu Wang, Beijing (CN); Yuge Chu, Beijing (CN); and Yi Zhang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/789,180
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 17, 2021, PCT No. PCT/CN2021/119097
§ 371(c)(1), (2) Date Jun. 25, 2022,
PCT Pub. No. WO2023/039842, PCT Pub. Date Mar. 23, 2023.
Prior Publication US 2024/0177661 A1, May 30, 2024
Int. Cl. G09G 3/3233 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 2300/0426 (2013.01); G09G 2310/061 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
K number of reset signal lines respectively configured to provide reset signals to reset transistors in K columns pixel driving circuits of the array substrate;
wherein the K number of reset signal lines comprises:
a plurality of third reset signal lines in (2k−1)-th columns of K columns, K and k being positive integers, 1≤ k≤ (K/2); and
a plurality of fourth reset signal lines in (2k)-th columns of the K columns;
wherein the array substrate comprises a first interconnected reset signal supply network and a second interconnected reset signal supply network;
wherein the first interconnected reset signal supply network comprises the plurality of third reset signal lines in the (2k−1)-th columns, and a plurality of first reset signal lines respectively cross over the plurality of third reset signal lines; and
the second interconnected reset signal supply network comprises the plurality of fourth reset signal lines in the (2k)-th columns, and a plurality of second reset signal lines respectively cross over the plurality of fourth reset signal lines;
wherein the array substrate further comprises a first initialization connecting line present in a (2k)-th column, and absent in a (2k−1)-th column and a second initialization connecting line present in the (2k−1)-th column, and absent in the (2k)-th column;
wherein the first initialization connecting line in the (2k)-th column connects a respective first reset signal line of the plurality of first reset signal lines and a source electrode of a first reset transistor in a respective pixel driving circuit in the (2k)-th column together;
the second initialization connecting line in the (2k−1)-th column connects a respective second reset signal line of the plurality of second reset signal lines and a source electrode of a second reset transistor in a respective pixel driving circuit in the (2k−1)-th column together;
a respective third reset signal line in the (2k−1)-th column connects a respective first reset signal line of the plurality of first reset signal lines and a source electrode of a first reset transistor in the respective pixel driving circuit in the (2k−1)-th column together; and
a respective fourth reset signal line in the (2k)-th column connects a respective second reset signal line of the plurality of second reset signal lines and a source electrode of a second reset transistor in the respective pixel driving circuit in the (2k)-th column together.