US 12,190,797 B2
Pixel and display apparatus of which static power consumption is reduced
Sung Ho Hwang, Seongnam-si (KR); Ji Haeng Lee, Seongnam-si (KR); Hye Min Bae, Seongnam-si (KR); and Dae Young Jung, Seongnam-si (KR)
Assigned to SAPIEN Semiconductors Inc., Gyeonggi-do (KR)
Filed by SAPIEN SEMICONDUCTORS INC., Seongnam-si (KR)
Filed on Oct. 31, 2023, as Appl. No. 18/498,244.
Application 18/498,244 is a continuation in part of application No. 17/946,601, filed on Sep. 16, 2022, granted, now 11,922,860.
Claims priority of application No. 10-2022-0055973 (KR), filed on May 6, 2022; and application No. 10-2022-0076549 (KR), filed on Jun. 23, 2022.
Prior Publication US 2024/0062714 A1, Feb. 22, 2024
Int. Cl. G09G 3/32 (2016.01)
CPC G09G 3/32 (2013.01) [G09G 2300/0842 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0251 (2013.01); G09G 2330/021 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A pixel driving circuit for driving a luminous element by a pulse width modulation (PWM) operation, the pixel driving circuit comprising:
a first memory configured to store multi-digit bit values of image data;
a driver connected to the luminous element and configured to control a power supply to the luminous element according to each bit value of the image data, wherein the driver including a capacitor for charging a voltage required for driving the luminous element;
a bias circuit configured to supply and not to supply power to the capacitor of the driver according to each bit value of the image data; and
a controller configured to:
control the bias circuit to supply the power to charge the capacitor when each digit of the image data stored in the first memory has a bit value of 1; and
control the bias circuit not to supply the power to the capacitor when each digit of the image data stored in the first memory has a bit value of 0.