| CPC G09G 3/32 (2013.01) [G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01); H01L 27/124 (2013.01)] | 20 Claims |
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1. A gate driving circuit comprising:
an N-th stage to output an N-th scan gate signal based on an N-th scan clock signal, a voltage of a QN node and a voltage of a QBN node, and to output an N-th carry signal based on an N-th carry clock signal, the voltage of the QN node and the voltage of the QBN node; and
an N+1-th stage to output an N+1-th scan gate signal based on an N+1-th scan clock signal, a voltage of a QN+1 node and the voltage of the QBN node, and to output an N+1-th carry signal based on an N+1-th carry clock signal, the voltage of the QN+1 node and the voltage of the QBN node,
wherein the N-th stage and the N+1-th stage share an inverting circuit,
wherein the inverting circuit controls the QBN node based on a third signal,
wherein N is a positive integer,
wherein the N-th stage further comprises a second pull down control circuit which outputs a first low voltage to the QBN node in response to a previous carry signal, and
wherein the N-th stage and the N+1-th stage share the second pull down control circuit.
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