US 12,190,781 B2
Shift register unit and driving method therefor, gate drive circuit, and display device
Zhu Wang, Beijing (CN); Zhenglong Yan, Beijing (CN); Hui Lu, Beijing (CN); Ke Liu, Beijing (CN); Ling Shi, Beijing (CN); and Yipeng Chen, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Chengdu (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/910,539
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Oct. 25, 2021, PCT No. PCT/CN2021/126087
§ 371(c)(1), (2) Date Sep. 9, 2022,
PCT Pub. No. WO2022/213579, PCT Pub. Date Oct. 13, 2022.
Claims priority of application No. 202110378872.1 (CN), filed on Apr. 8, 2021.
Prior Publication US 2024/0203316 A1, Jun. 20, 2024
Int. Cl. G09G 3/20 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G11C 19/28 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A shift register unit, comprising:
a first input circuit coupled to a first clock terminal, a first node, a second node, a third node, a pull-up power supply terminal, and a pull-down power supply terminal, wherein the first input circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the first node and control the pull-down power supply terminal to be conducted or non-conducted with the first node in response to a first clock signal provided by the first clock terminal; and control the pull-up power supply terminal to be conducted or non-conducted with the third node and control the pull-down power supply terminal to be conducted or non-conducted with the third node in response to a potential of the second node;
a second input circuit coupled to the first node, the second node, the third node, the pull-up power supply terminal, the pull-down power supply terminal, an input control terminal, and the first clock terminal, wherein the second input circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the second node and control the pull-down power supply terminal to be conducted or non-conducted with the second node in response to a potential of the first node, a potential of the third node, the first clock signal, and an input control signal provided by the input control terminal; and
an output circuit coupled to the pull-up power supply terminal, the pull-down power supply terminal, the third node, a second clock terminal, and an output terminal, wherein the output circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the output terminal and control the pull-down power supply terminal to be conducted or non-conducted with the output terminal in response to the potential of the third node and a second clock signal provided by the second clock terminal;
wherein the output circuit comprises a first output sub-circuit and a second output sub-circuit; wherein
the first output sub-circuit is coupled to the second clock terminal, the third node, the pull-up power supply terminal, the pull-down power supply terminal, and a fourth node, and is configured to control the pull-up power supply terminal to be conducted or non-conducted with the fourth node and control the pull-down power supply terminal to be conducted or non-conducted with the fourth node in response to the second clock signal and the potential of the third node; and
the second output sub-circuit is coupled to the fourth node, the pull-up power supply terminal, the pull-down power supply terminal, and the output terminal, and is configured to control the pull-up power supply terminal to be conducted or non-conducted with the output terminal and control the pull-down power supply terminal to be conducted or non-conducted with the output terminal in response to a potential of the fourth node;
wherein the second output sub-circuit comprises an odd number of fourth output transistors connected in series between the fourth node and the output terminal; wherein
each of the fourth output transistors is a CMOS transistor, and two first electrodes of each of the fourth output transistors are coupled to the pull-up power supply terminal and the pull-down power supply terminal, respectively; and
a channel width-to-length ratio of at least one of the fourth output transistors is greater than channel width-to-length ratios of transistors in the shift register unit except the at least one of the fourth output transistors.