US 12,190,780 B2
GOA circuit and display panel
Tuo Feng, Shenzhen (CN); and Xianjin Ge, Shenzhen (CN)
Assigned to SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 17/600,332
Filed by SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Shenzhen (CN)
PCT Filed Sep. 8, 2021, PCT No. PCT/CN2021/117083
§ 371(c)(1), (2) Date Sep. 30, 2021,
PCT Pub. No. WO2022/252427, PCT Pub. Date Dec. 8, 2022.
Claims priority of application No. 202110610625.X (CN), filed on Jun. 1, 2021.
Prior Publication US 2024/0046844 A1, Feb. 8, 2024
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A gate driver on array GOA circuit, comprising a plurality of GOA units, which is cascaded, and a nth stage GOA unit comprises:
a pull-up control module, outputting a pull-up control signal of a high potential according to a n−bth stage transfer signal and a n−bth stage gate drive signal when scanning starts;
an output module, outputting a nth stage gate drive signal of the high potential according to the pull-up control signal of the high potential and a nth stage non-inverting clock signal;
a pull-down module, pulling down the pull-up control signal outputted by the pull-up control module and the nth stage gate drive signal outputted by the output module to a low potential according to a n+bth stage gate drive signal when the scanning is completed; and
a pull-down maintaining module, maintaining the pull-up control signal outputted by the pull-up control module and the nth stage gate drive signal outputted by the output module at the low potential according to the nth stage non-inverting clock signal and a nth stage inverting clock signal, wherein the nth stage non-inverting clock signal and the nth stage inverting clock signal are mutually inverted signals.