US 12,190,435 B2
Enhanced techniques for traversing ray tracing acceleration structures
Gregory Muthler, Austin, TX (US); and John Burgess, Austin, TX (US)
Assigned to NVIDIA CORPORATION, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Oct. 10, 2023, as Appl. No. 18/483,762.
Application 18/483,762 is a continuation of application No. 17/829,954, filed on Jun. 1, 2022, granted, now 11,816,783.
Application 17/829,954 is a continuation of application No. 16/898,980, filed on Jun. 11, 2020, granted, now 11,380,041, issued on Jul. 5, 2022.
Prior Publication US 2024/0037841 A1, Feb. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 15/06 (2011.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06T 15/08 (2011.01); G06T 17/00 (2006.01)
CPC G06T 15/06 (2013.01) [G06F 9/30094 (2013.01); G06F 9/5027 (2013.01); G06T 15/08 (2013.01); G06T 17/005 (2013.01); G06T 2210/12 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A ray tracing acceleration hardware device, comprising:
memory configured to store at least portions of an acceleration data structure comprising a compressed treelet including a node, one or more child nodes of the node, and a state indicator associated with the node;
ray storage configured to store an operation indicator from a ray received from a processor;
traversal circuitry configured to traverse the acceleration data structure according to the ray, the traversing including, at a node of the acceleration data structure, (a) performing an operation specified by the operation indicator if the state indicator is in a first state, and (b) ignoring the operation if the state indicator is in a second state; and
intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor.