	US 12,190,406 B2
	Pointer de-referencing technologies
Raghavendra Kamath Miyar, Bangalore (IN); Rajalakshmi Athimoolam, Tenkasi (IN); Subramaniam Maiyuran, Gold River, CA (US); Jorge F. Garcia Pabon, Folsom, CA (US); Rajarshi Bajpayee, Bangalore (IN); and Krishan Malik, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 26, 2021, as Appl. No. 17/359,528.
Prior Publication US 2022/0414818 A1, Dec. 29, 2022
Int. Cl. G06T 1/60 (2006.01); G06T 1/20 (2006.01)

CPC G06T 1/60 (2013.01) [G06T 1/20 (2013.01)]

23 Claims

1. An apparatus comprising:

at least one memory and

at least one processor, wherein the at least one processor is to:

represent at least one vertex in a set of vertices of a first polygon using a first index;

store the first index into the at least one memory; and

indicate whether the first index is to be de-referenced based on a comparison between the first index and at least one other index, wherein:

a first memory pointer is associated with the at least one vertex in the set of vertices of the first polygon and

the first index comprises a number of bits that is less than a number of bits associated with the first memory pointer.