US 12,190,157 B2
Methods, systems, and apparatuses for scalable port-binding for asymmetric execution ports and allocation widths of a processor
Daeho Seo, Austin, TX (US); Vikash Agarwal, Austin, TX (US); John Esper, Austin, TX (US); Khary Alexander, Cedar Park, TX (US); Asavari Paranjape, Austin, TX (US); and Jonathan Combs, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 26, 2020, as Appl. No. 17/033,739.
Prior Publication US 2022/0100569 A1, Mar. 31, 2022
Int. Cl. G06F 9/46 (2006.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01)
CPC G06F 9/5027 (2013.01) [G06F 9/30145 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A hardware processor core comprising:
a decoder circuit to decode instructions into micro-operations;
an instruction decode queue to store the micro-operations;
a plurality of different types of execution circuits that each comprise a respective input port and a respective input queue; and
an allocation circuit comprising a plurality of allocation lanes coupled to the instruction decode queue and to the input ports of the plurality of different types of execution circuits, wherein the allocation circuit is to, for an input of the micro-operations on the plurality of allocation lanes, generate a sorted list of occupancy of the input queues of each input port, generate a pre-binding mapping of the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes in a circular order according to the sorted list, when a type of micro -operation from an allocation lane does not match a type of execution circuit of an input port in the pre-binding mapping, slide the pre-binding mapping so that the input port maps to a next allocation lane having a matching type of micro -operation to generate a final mapping of the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes, and bind the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes according to the final mapping.