| CPC G06F 9/4881 (2013.01) [G06F 9/485 (2013.01)] | 20 Claims |
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1. An apparatus, comprising:
processor circuitry configured to execute operations for multiple threads, wherein the processor circuitry includes:
a plurality of channel pipelines for a plurality of channels, wherein the channel pipeline for a given channel includes multiple pipeline stages, including a decode stage configured to identify one or more execution pipelines targeted by a given instruction;
a plurality of execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines;
first scheduler circuitry configured to arbitrate among threads, prior to the decode stages of the channel pipelines, to assign threads to channels based on priorities assigned to the threads; and
second scheduler circuitry configured to arbitrate among channels to assign an operation from a given channel to a given execution pipeline, wherein the assignment is based on decode of the operation by the decode stage and wherein the arbitration is among a greater number of operations output by the channel pipelines than a number of available execution pipelines configured to perform the operations;
wherein one or more of the plurality of execution pipelines are configured to provide backpressure information to the first scheduler circuitry based on execution status; and
wherein the first scheduler circuitry is configured to adjust priority of an incoming thread for arbitration of the incoming thread by the first scheduler circuitry for assignment to a channel based on the backpressure information.
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