US 12,190,118 B2
Data locality enhancement for graphics processing units
Christopher J. Hughes, Santa Clara, CA (US); Prasoonkumar Surti, Folsom, CA (US); Guei-Yuan Lueh, San Jose, CA (US); Adam T. Lake, Portland, OR (US); Jill Boyce, Portland, OR (US); Subramaniam Maiyuran, Gold River, CA (US); Lidong Xu, Beijing (CN); James M. Holland, Folsom, CA (US); Vasanth Ranganathan, El Dorado Hills, CA (US); Nikos Kaburlasos, Folsom, CA (US); Altug Koker, El Dorado Hills, CA (US); and Abhishek R. Appu, El Dorado Hills, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Jun. 22, 2023, as Appl. No. 18/339,454.
Application 18/339,454 is a continuation of application No. 17/095,585, filed on Nov. 11, 2020, granted, now 11,726,793.
Claims priority of provisional application 62/935,716, filed on Nov. 15, 2019.
Prior Publication US 2023/0418617 A1, Dec. 28, 2023
Int. Cl. G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06F 12/084 (2016.01); G06T 1/60 (2006.01)
CPC G06F 9/3891 (2013.01) [G06F 9/5066 (2013.01); G06F 9/544 (2013.01); G06F 12/084 (2013.01); G06T 1/60 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
processor circuitry coupled to a memory, the processor circuitry to:
map one or more tasks to one or more processing resources; and
forward one or more destination identifiers corresponding to the one or more tasks to the one or more processing resources, wherein the one or more tasks are represented in a task graph, and receive data dependencies associated with the one or more tasks including one or more producer tasks or one or more consumer tasks.