US 12,190,114 B2
Segmented branch target buffer based on branch instruction type
Niranjan Kumar Soundararajan, Karnataka (IN); Sreenivas Subramoney, Bangalore (IN); and Sr Swamy Saranam Chongala, Andhra Pradesh (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2020, as Appl. No. 17/130,016.
Prior Publication US 2022/0197657 A1, Jun. 23, 2022
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3806 (2013.01) [G06F 9/3844 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A processor comprising:
a branch predictor to predict whether a branch instruction is to be taken; and
a branch target buffer (BTB) coupled to the branch predictor, the BTB segmented into:
a first cache portion comprising a target cache portion to store target prediction information for indirect branch instructions and infrequent direct branch instructions; and
a second cache portion comprising:
a first sub-cache portion to store target prediction information for direct branch instructions having a target address within a same page as the branch instruction;
a second sub-cache portion to store target prediction information for direct branch instructions having a target address within a different page from the branch instruction, wherein the second sub-cache portion comprises:
a first portion to store a page portion of the target prediction information; and
a second portion to store offset information of the target prediction information;
wherein, in response to an indication that the branch instruction is to be taken, the BTB is to access an entry in one of the first cache portion and the second cache portion based at least in part on a type of the branch instruction, the type of the branch instruction comprising whether the branch instruction is a direct branch instruction or an indirect branch instruction, an occurrence frequency of the branch instruction, and spatial information regarding a distance between a target address of a target of the branch instruction and an address of the branch instruction.