US 12,190,084 B2
Fracturable data path in a reconfigurable data processor
Raghu Prabhakar, San Jose, CA (US); and David Brian Jackson, Dana Point, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Jan. 19, 2023, as Appl. No. 18/099,218.
Claims priority of provisional application 63/301,465, filed on Jan. 20, 2022.
Prior Publication US 2023/0229623 A1, Jul. 20, 2023
Int. Cl. G06F 8/41 (2018.01); G06F 9/30 (2018.01); G06F 9/445 (2018.01); G06F 15/80 (2006.01)
CPC G06F 8/441 (2013.01) [G06F 9/3001 (2013.01); G06F 9/44505 (2013.01); G06F 15/80 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A coarse-grained reconfigurable (CGR) processor comprising:
an array of configurable units including a first configurable unit, the first configurable unit comprising a multi-port memory having a first address input associated with a first access port of the multi-port memory and a second address input associated with a second access port of the multi-port memory, and a fracturable data path with a plurality of sub-paths configurable to generate addresses for the multi-port memory:
the fracturable data path comprising:
a plurality of stages, including an initial stage, one or more intermediate stages, and a final stage, each stage of the plurality of stages respectively including an arithmetic logic unit (ALU), selection logic to select two or more inputs for the ALU, and sub-path pipeline registers;
a first output, coupled to a first address input of the multi-port memory, configurable to provide first data selected from any one of the sub-path pipeline registers; and
a second output, coupled to a second address input of the multi-port memory configurable to provide second data, different from the first data, selected from any one of the sub-path pipeline registers;
the first configurable unit further comprising a configuration store to store configuration data including first immediate data, second immediate data, selection information for the selection logic, and ALU configuration information respectively for each stage of the plurality of stages, and output selection information to select the first data and the second data for the first output and the second output, respectively.