US 12,190,077 B2
Method and apparatus for eliminating inter-link skew in high-speed serial data communications
Sai Ram Venkata Pattabhi Nedunuri, Hyderabad (IN); and Killivalavan Kaliyamoorthy, Cuddalore (IN)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Nov. 23, 2022, as Appl. No. 17/993,464.
Prior Publication US 2024/0168710 A1, May 23, 2024
Int. Cl. G06F 5/06 (2006.01); G06F 1/10 (2006.01); H04L 25/02 (2006.01)
CPC G06F 5/06 (2013.01) [G06F 1/10 (2013.01); H04L 25/0272 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of link circuits each configured to receive serial data over one or more input serial links, the plurality of link circuits including a primary link circuit and a secondary link circuit, wherein the secondary link circuit comprises:
a de-serializer circuit configured to receive the serial data from the one or more input serial links and convert the serial data into parallel data; and
an aligner circuit comprising a memory, the aligner circuit configured to:
stop at least one of storing the parallel data in the memory and reading the memory based on a channel bonding signal generated based on a channel bonding symbol within the serial data;
output the channel bonding signal to a finite state machine (FSM) circuit of the primary link circuit and pause reading the memory; and
resume reading the memory and output the parallel data based on receiving a read signal from the FSM circuit of the primary link circuit.