US 12,190,039 B1
Incremental clock tree planning
Prashant Gupta, Karnataka (IN); Shibaji Banerjee, Karnataka (IN); and Suhasini Rege, Karnataka (IN)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Feb. 16, 2022, as Appl. No. 17/673,516.
Int. Cl. G06F 30/396 (2020.01); G06F 30/392 (2020.01); G06F 111/04 (2020.01)
CPC G06F 30/396 (2020.01) [G06F 30/392 (2020.01); G06F 2111/04 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving an integrated circuit design including a plurality of sub-circuits and one or more clocks to be distributed to the sub-circuits;
setting one or more constraints on generating a clock network for a selected clock of the one or more clocks of the integrated circuit design;
building, by a processor, a clock tree graph for the clock network for the selected clock based on a cached initial clock tree graph stored in a memory connected to the processor, the clock tree graph comprising a plurality of nodes corresponding to the sub-circuits of the integrated circuit design;
generating, a pin topology for the clock network based on the clock tree graph and the integrated circuit design; and
placing, based on the pin topology, one or more pins for the clock network at one or more sides of the sub-circuits within the integrated circuit design to generate a pin placement for the clock network.