US 12,190,034 B2
Logic circuits with reduced transistor counts
Chi-Lin Liu, Hsinchu (TW); Jerry Chang-Jui Kao, Hsinchu (TW); Wei-Hsiang Ma, Hsinchu (TW); Lee-Chung Lu, Hsinchu (TW); Fong-Yuan Chang, Hsinchu (TW); Sheng-Hsiung Chen, Hsinchu (TW); and Shang-Chih Hsieh, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,938.
Application 18/362,938 is a division of application No. 17/340,662, filed on Jun. 7, 2021, granted, now 11,755,798.
Application 17/340,662 is a continuation of application No. 15/930,010, filed on May 12, 2020, granted, now 11,030,366, issued on Jun. 8, 2021.
Application 15/930,010 is a continuation of application No. 15/936,712, filed on Mar. 27, 2018, granted, now 10,664,565, issued on May 26, 2020.
Claims priority of provisional application 62/509,048, filed on May 19, 2017.
Prior Publication US 2023/0376661 A1, Nov. 23, 2023
Int. Cl. G06F 30/327 (2020.01); G06F 111/06 (2020.01); G06F 119/18 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 2111/06 (2020.01); G06F 2119/18 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A logic circuit for providing a multibit flip-flop (MBFF) function, the logic circuit comprising:
a first inverter configured to receive a clock signal and generate a corresponding clock_bar signal;
a second inverter configured to receive the clock_bar signal and generate a corresponding clock_bar_bar signal;
a third inverter configured to receive a control signal and generate a corresponding control_bar signal; and
a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each TXFF circuit including:
a NAND circuit configured to receive data signals; and
a 1-bit transmit gate flip-flop (TGFF) circuit configured to:
output signals Q and q; and
receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar signal, the clock_bar_bar signal, the control signal and the control_bar signal; and
a first one of the TXFF circuits in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.