	US 12,189,996 B2
	Multiple register clock driver loaded memory subsystem
Matthew B. Leslie, Boise, ID (US); Timothy M. Hollis, Boise, ID (US); and Roy E. Greeff, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Oct. 19, 2023, as Appl. No. 18/490,589.
Application 18/490,589 is a continuation of application No. 17/360,943, filed on Jun. 28, 2021, granted, now 11,797,229.
Claims priority of provisional application 63/047,407, filed on Jul. 2, 2020.
Prior Publication US 2024/0045620 A1, Feb. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 1/04 (2006.01); G06F 13/16 (2006.01)

CPC G06F 3/0659 (2013.01) [G06F 1/04 (2013.01); G06F 13/1689 (2013.01); G06F 2213/16 (2013.01)]

20 Claims

1. An apparatus comprising:

a first semiconductor package comprising a first register clock driver and a first memory, the first register clock driver configured to provide first command and address information to the first memory responsive to a clock signal and the first memory configured to perform a memory access operation in response to the first command and address information; and

a second semiconductor package comprising a second register clock driver and a second memory, the second register clock driver configured to provide the second command and address information to the second memory responsive to the clock signal, the second memory is configured to perform a memory access operation in response to the second command and address information.