US 12,189,994 B2
Fuse latch of semiconductor device for latching data of a repair fuse cell
Jae Hwan Seo, Icheon-si (KR); and Chul Moon Jung, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 5, 2024, as Appl. No. 18/432,663.
Application 18/432,663 is a division of application No. 17/557,009, filed on Dec. 20, 2021, granted, now 11,928,362.
Claims priority of application No. 10-2021-0112084 (KR), filed on Aug. 25, 2021.
Prior Publication US 2024/0176545 A1, May 30, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A fuse latch of a semiconductor device comprising:
first and second NMOS transistors, each of which receives a first control signal through a gate terminal and transmits fuse cell data in response to the first control signal;
a first inverter configured to include a first PMOS transistor and a third NMOS transistor coupled in series between a power supply voltage terminal and a ground voltage terminal, with an input node of the first inverter coupled to the second NMOS transistor and an output node of the first inverter coupled to the first NMOS transistor;
a second inverter configured to include a second PMOS transistor and a fourth NMOS transistor coupled in series between the power supply voltage terminal and the ground voltage terminal, with an input node of the second inverter coupled to the output node of the first inverter and an output node of the second inverter coupled to the input node of the first inverter;
a fifth NMOS transistor, with a gate terminal coupled to the input node of the first inverter and the output node of the second inverter and with a first terminal coupled to a data output terminal; and
a sixth NMOS transistor configured to receive a second control signal through a gate terminal and to selectively couple the ground voltage terminal to a second terminal of the fifth NMOS transistor in response to the second control signal,
wherein
a portion of the second NMOS transistor and a portion of the fourth NMOS transistor are included in a first active region;
a portion of the second PMOS transistor is included in a second active region;
a portion of the first PMOS transistor is included in a third active region;
a portion of the first NMOS transistor and a portion of the third NMOS transistor are included in a fourth active region;
a portion of the fifth NMOS transistor and a portion of the sixth NMOS transistor are included in a fifth active region; and
the first active region, the second active region, the third active region, the fourth active region, and the fifth active region are sequentially arranged in a first direction.