US 12,189,993 B2
Memory devices for suspend and resume operations
Umberto Siciliani, Rubano (IT); and Floriano Montemurro, Albignasego (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jan. 9, 2024, as Appl. No. 18/407,876.
Application 18/407,876 is a continuation of application No. 17/382,615, filed on Jul. 22, 2021, granted, now 11,907,574.
Claims priority of provisional application 63/131,825, filed on Dec. 30, 2020.
Prior Publication US 2024/0143235 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 9/48 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/061 (2013.01); G06F 3/0679 (2013.01); G06F 9/485 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
an array of memory cells; and
a controller configured to access the array of memory cells,
wherein the controller is further configured to:
receive a command to perform an erase operation;
in response to the command to perform the erase operation, begin execution of the erase operation;
in response to executing the erase operation, pull down a ready/busy control signal to indicate the memory device is busy executing the erase operation;
while executing the erase operation, receive a command to perform a program operation with the ready/busy control signal pulled down;
in response to the command to perform the program operation, suspend the execution of the erase operation while keeping the ready/busy control signal pulled down; and
with the execution of the erase operation suspended and with the ready/busy control signal pulsed down, execute the program operation while keeping the ready/busy control signal pulled down.