US 12,189,991 B2
Storage device controller and method capable of allowing incoming out-of-sequence write command signals
Li-Chi Chen, Taichung (TW); and Yen-Yu Jou, Taoyuan (TW)
Assigned to Silicon Motion, Inc., Hsinchu County (TW)
Filed by Silicon Motion, Inc., Hsinchu County (TW)
Filed on Oct. 2, 2022, as Appl. No. 17/958,430.
Prior Publication US 2024/0111456 A1, Apr. 4, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A storage device controller, comprising:
an interface circuit, coupled to a host device externally coupled to the storage device controller, for receiving and storing different write address information of different write command signals sent from the host device, the different write address information being out of sequence; and
multiple processor cores, coupled to the interface circuit, a manager core of the multiple processor cores being used for rearranging an order of the different write command signals in sequence based on the different write address information and then writing data into at least one storage zone according to the rearranged different write command signals;
wherein the multiple processor cores comprise:
a first processor core, capable of being used as the manager core for all storage zones; and
at least one second processor core each capable of being used as a worker core;
wherein the first processor core controls the at least one second processor core writing data into the at least one storage zone according to the different write address information rearranged in sequence; and, the first processor core executes a manager thread to rearrange the order of the different write command signals based on the different write address information and controls the at least one second processor core writing corresponding data units into corresponding storage spaces of at least one storage zone according to the rearranged different write command signals.