US 12,189,989 B2
Memory device queuing a plurality of commands and memory system having memory device
Byoung Sung You, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jul. 27, 2021, as Appl. No. 17/443,711.
Application 17/443,711 is a continuation in part of application No. 15/961,031, filed on Apr. 24, 2018, granted, now 11,099,776.
Claims priority of application No. 10-2017-0121096 (KR), filed on Sep. 20, 2017.
Prior Publication US 2021/0357155 A1, Nov. 18, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0634 (2013.01); G06F 3/0679 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory device comprising a device queue and a buffer; and
a memory controller configured to communicate with the memory device through a corresponding way among a plurality of ways and include a plurality of way command queues respectively corresponding to the plurality of ways,
wherein the device queue queues a plurality of commands received from a corresponding way command queue among the plurality of way command queues, and
wherein the memory device performs an internal operation at least including continuously performing a plurality of read operations respectively corresponding to a plurality of read commands queued in the device queue to store read data respectively corresponding to the plurality of read operations in the buffer and then outputs all of the read data from the buffer to the memory controller after continuously performing the plurality of read operations, under control of the memory controller.