US 12,189,988 B2
Write broadcast operations associated with a memory device
Dmitri A. Yudanov, Rancho Cordova, CA (US); and Shanky Kumar Jain, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/414,298
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Dec. 20, 2019, PCT No. PCT/US2019/067844
§ 371(c)(1), (2) Date Jun. 15, 2021,
PCT Pub. No. WO2020/132438, PCT Pub. Date Jun. 25, 2020.
Claims priority of provisional application 62/783,388, filed on Dec. 21, 2018.
Prior Publication US 2022/0020424 A1, Jan. 20, 2022
Int. Cl. G11C 11/406 (2006.01); G06F 3/06 (2006.01); G06F 9/54 (2006.01); G06F 12/02 (2006.01); G06F 12/0802 (2016.01); G06F 12/0873 (2016.01); G06F 12/0875 (2016.01); G06F 12/0893 (2016.01); G06F 12/1045 (2016.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01); G11C 11/22 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 9/546 (2013.01); G06F 12/0246 (2013.01); G06F 12/0802 (2013.01); G06F 12/0873 (2013.01); G06F 12/0875 (2013.01); G06F 12/0893 (2013.01); G06F 12/1045 (2013.01); G11C 7/08 (2013.01); G11C 7/1012 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 8/08 (2013.01); G11C 11/221 (2013.01); G11C 11/2257 (2013.01); G11C 11/2259 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/2297 (2013.01); G11C 11/406 (2013.01); G11C 11/40603 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G06F 2212/60 (2013.01); G06F 2212/608 (2013.01); G06F 2212/72 (2013.01); G06F 2212/7201 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method, comprising:
determining a pattern of logic states for storing in a memory device;
storing, at a first component of the memory device, a plurality of signal states associated with the pattern of logic states;
determining, at a second component of the memory device, a plurality of locations for storing the pattern of logic states, wherein each location of the plurality of locations is associated with a respective word line of a plurality of word lines;
transferring, via the first component, data associated with the pattern of logic states from at least one location of the plurality of locations to a sense component array based at least in part on the determining of the plurality of locations; and
writing the pattern of logic states to the plurality of locations of the second component based at least in part on the plurality of signal states stored at the first component and concurrently activating multiple word lines of the plurality of word lines.