US 12,189,987 B2
Processing-in-memory (PIM) devices
Choung Ki Song, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jul. 30, 2021, as Appl. No. 17/390,499.
Application 17/390,499 is a continuation in part of application No. 17/002,341, filed on Aug. 25, 2020, granted, now 11,720,441.
Claims priority of application No. 10-2019-0117098 (KR), filed on Sep. 23, 2019.
Prior Publication US 2021/0357154 A1, Nov. 18, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 7/499 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 11/10 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 7/49915 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 11/1068 (2013.01)] 20 Claims
OG exemplary drawing
 
15. A processing-in-memory (PIM) device comprising:
an error correction code (ECC) logic circuit configured to generate first data from read data and read parity received from a storage region, based on control of an operation control circuit when a read operation in an operation mode is performed;
a global buffer configured to store second data; and
a multiplication and accumulation (MAC) circuit configured to perform:
a comparison operation,
a multiplication operation, or,
an addition operation,
the comparison operation, the multiplication operation and the addition operation being selectively performed by the MAC circuit on the first data and the second data, responsive to a reference value data to generate a MAC operation result when a MAC operation is performed.