US 12,189,986 B2
Methods and systems for software based prefetching for low buffer depth sequential read traffic
Arun Athreya, Folsom, CA (US); Mariusz Dolny, Gdańsk (PL); Bartosz Kot, Gdańsk (PL); Michał Mamczyński, Gdynia (PL); Shivashekar Muralishankar, Folsom, CA (US); Shankar Natarajan, Folsom, CA (US); and Yihua Zhang, Folsom, CA (US)
Assigned to SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed by SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed on Feb. 12, 2024, as Appl. No. 18/438,886.
Application 18/438,886 is a continuation of application No. 18/091,061, filed on Dec. 29, 2022, granted, now 12,067,284.
Prior Publication US 2024/0220157 A1, Jul. 4, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, by control circuitry while the control circuitry executes a storage device driver of a storage device, at least one read instruction of a stream of read instructions;
determining, by control circuitry, whether the at least one read instruction is part of a sequential stream of read instructions;
in response to the determination that the at least one read instruction is not part of a sequential stream of read instructions:
issuing, by control circuitry, an independent plane read operation to access memory of the storage device across at least two planes of the memory;
in response to the determination that the at least one read instruction is part of a sequential stream of read instructions:
determining, by control circuitry, whether the storage device has a cache read feature available;
in response to the determination that the storage device has a cache read feature available:
issuing, by control circuitry, a multi-plane sequential read command to access the memory across the at least two planes; and
in response to the determination that the storage device does not have a cache read feature available:
issuing, by control circuitry, an independent plane read operation to access memory of the storage device across the at least two planes;
predicting addresses across the at least two planes of the memory that are to be accessed based on an analysis of the stream of read instructions;
accessing data located at the predicted addresses; and
executing the at least one read instruction of the stream of read instructions using at least the accessed data.