| CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 11/3672 (2013.01)] | 21 Claims |
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1. A system to support test case generation for a device under test (DUT), comprising:
a testbench device configured to
a) select a pair of processors from a plurality of processors of the DUT for testing one pair of processors from the plurality of processors at a time, wherein a first processor of the pair of processors is a requester requesting access to a cache associated with a second processor of the pair of processors, wherein the second processor is a snooped requester;
b) automatically generate a set of test cases for memory coherence testing of the pair of processors based on an algorithm-driven script, wherein the set of test cases includes an instruction set for at least one of the first processor or the second processor and a set of valid combinations of cache states of caches associated with the requester and the snooped requester, respectively;
c) enable the instruction set to be executed by at least one of the first processor or the second processor to validate memory coherence of the pair of processors; and
d) repeat steps a) to c) above until each processor of the plurality of processors is included for memory coherence testing at least once.
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