US 12,189,976 B2
Apparatus for outputting internal state of memory apparatus and memory system using the apparatus
Seong-Hoon Woo, Hwaseong-si (KR); Hak-Sun Kim, Suwon-si (KR); Kwang-Jin Lee, Hwaseong-si (KR); and Su-Chang Jeon, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 10, 2023, as Appl. No. 18/506,293.
Application 18/506,293 is a continuation of application No. 17/231,734, filed on Apr. 15, 2021, granted, now 11,847,339.
Application 17/231,734 is a continuation of application No. 16/503,116, filed on Jul. 3, 2019, granted, now 11,003,382, issued on May 11, 2021.
Application 16/503,116 is a continuation of application No. 15/678,759, filed on Aug. 16, 2017, granted, now 10,346,087, issued on Jul. 9, 2019.
Claims priority of application No. 10-2016-0103752 (KR), filed on Aug. 16, 2016.
Prior Publication US 2024/0078034 A1, Mar. 7, 2024
Int. Cl. G11C 7/20 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 16/20 (2006.01); G11C 16/32 (2006.01); G11C 16/04 (2006.01)
CPC G06F 3/0653 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 13/16 (2013.01); G11C 7/1063 (2013.01); G11C 7/20 (2013.01); G11C 7/22 (2013.01); G11C 16/20 (2013.01); G11C 16/32 (2013.01); G11C 16/0483 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory system comprising:
a plurality of memory chips in each of which a first state output pin is arranged; and
a memory controller in which a first state input pin connected in a wired-AND configuration to each first state output pin arranged in the plurality of memory chips, the memory controller being configured to transmit at least one of a chip enable signal or an initially set function command to the plurality of memory chips,
wherein each of the plurality of memory chips outputs a first signal having one level from among three logic levels based on at least one of the chip enable signal or the initially set function command, and
wherein the memory controller is further configured to receive a second signal through the first state input pin as a result of an AND operation of first signals output through the first state output pins.