CPC G06F 3/0622 (2013.01) [G06F 3/0637 (2013.01); G06F 3/0679 (2013.01)] | 16 Claims |
1. An I/O memory management unit for use in a computer architecture having a processor communicating with a main computer memory having memory addresses and an I/O device having I/O device addresses, the I/O memory management unit comprising circuitry operating to:
(a) receive from the I/O device an I/O device address previously sent to the I/O device in a request from the processor;
(b) communicate with a data structure held in the main computer memory to match the I/O device address to permission data authorizing or not authorizing access to the I/O device address;
(c) output the permission data to the I/O device;
(d) receive from the I/O device a memory address for data transfer with the I/O device;
(e) communicate with a second data structure held in the main computer memory to match the memory address to second permission data authorizing or not authorizing access to the memory address; and
(f) output the second permission data to the I/O device.
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