US 12,189,961 B2
Charge loss mitigation through dynamic programming sequence
Yu-Chung Lien, San Jose, CA (US); and Zhenming Zhou, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Aug. 17, 2022, as Appl. No. 17/889,873.
Prior Publication US 2024/0061588 A1, Feb. 22, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0644 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A system comprising:
a memory device, and
a processing device, operatively coupled with the memory device, to perform operations comprising:
receiving a program command specifying new data to be programmed to the memory device;
partitioning the new data into a plurality of data partitions;
for a specified block of the memory device, identifying a wordline addressing a first set of memory cells to be programmed with a data partition of the plurality of data partitions;
reading existing data stored by a second set of memory cells, wherein the second set of memory cells is addressable by an adjacent wordline of the identified wordline;
for each data partition of the plurality of data partitions and based on the existing data, producing a plurality of expected data state metrics by determining a respective expected data state metric exhibited by the first set of memory cells of the identified wordline if the first set of memory cells is programmed with the data partition;
identifying a data partition associated with a lowest expected data state metric among the plurality of expected data state metrics; and
programming the identified data partition to the identified wordline.