| CPC G06F 3/0613 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
|
1. A memory sub-system comprising:
a memory sub-system controller comprising a plurality of controller channels;
one or more memory devices comprising a plurality of memory channels, wherein the one or more memory devices comprise a plurality of memory dies, wherein each memory channel of the plurality of memory channels corresponds to a respective one of the plurality of memory dies; and
a channel switch circuit coupled between the plurality of the controller channels and the plurality of memory channels, wherein each controller channel of the plurality of the controller channels is capable to be mapped to the plurality of memory channels for data routing the channel switch circuit comprising command processing logic configured to:
receive, from the memory sub-system controller, a plurality of channel mappings, wherein a first channel mapping of the plurality of channel mappings identifies a first controller channel of the plurality of controller channels and one or more first memory channels of the plurality of memory channels, and wherein a second channel mapping of the plurality of channel mappings identifies a second controller channel of the plurality of controller channels and one or more second memory channels of the plurality of memory channels; and
route, concurrently, data from the first controller channel of the plurality of controller channels to the one or more first memory channels of the plurality of memory channels that are associated with the first controller channel by the first channel mapping of the plurality of channel mappings, and data from the second controller channel of the plurality of controller channels to the one or more second memory channels of the plurality of memory channels that are associated with the second controller channel by the second channel mapping of the plurality of channel mappings.
|