| CPC G06F 3/0611 (2013.01) [G06F 3/064 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
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1. A memory device comprising:
a controller to program a multi-level cell (MLC) memory, including to:
sample a portion of the MLC memory using a series of program pulses with increasing magnitude of voltage;
follow each program pulse with a series of program verifies to compare a voltage level of cells in the portion of the MLC memory against corresponding program verify threshold voltage levels until a minimum program pulse voltage to start to program the MLC memory is reached; and
skip all but one or more lower level program verifies in the series of program verifies to reduce a time until the minimum program pulse voltage is reached.
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