| CPC G06F 3/061 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] | 25 Claims |
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1. A memory device, comprising:
a volatile memory;
a non-volatile memory; and
a controller configured to:
receive a command to read data in a first format from the non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format;
provide the plurality of copies of the data from the non-volatile memory to an error correction circuit;
compare, using the error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data;
store the dominant bit state for the bits of the data in the volatile memory as corrected data in the first format;
provide the corrected data from the volatile memory to the non-volatile memory; and
cause the corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.
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