US 12,189,948 B2
Device and method to minimize off-chip access between host and peripherals
Seongwook Park, Suwon-si (KR); Deok Jae Oh, Suwon-si (KR); Youngsam Shin, Suwon-si (KR); Yeongon Cho, Suwon-si (KR); and Yongmin Tai, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 28, 2023, as Appl. No. 18/191,254.
Claims priority of application No. 10-2022-0138697 (KR), filed on Oct. 25, 2022.
Prior Publication US 2024/0134522 A1, Apr. 25, 2024
Prior Publication US 2024/0231614 A9, Jul. 11, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0608 (2013.01) [G06F 3/064 (2013.01); G06F 3/0658 (2013.01); G06F 3/0673 (2013.01); G06F 12/0223 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A near-memory processing unit, comprising:
a compressor configured to, in response to a swap-out command received from a host, compress a page disposed in a normal memory space of a memory to obtain a compressed page, wherein the near-memory processing unit is separated from the host; and
a memory controller configured to, in response to the swap-out command, store the compressed page in a compressed memory space.