US 12,189,830 B2
Integrated circuit for security of a physically unclonable function and a device including the same
Bohdan Karpinskyy, Suwon-si (KR); Yong-ki Lee, Yongin-si (KR); Ji-eun Park, Suwon-si (KR); Kyoung-moon Ahn, Seoul (KR); and Yun-hyeok Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 23, 2022, as Appl. No. 17/847,593.
Application 17/847,593 is a continuation of application No. 16/553,318, filed on Aug. 28, 2019, granted, now 11,403,432.
Claims priority of application No. 10-2018-0174127 (KR), filed on Dec. 31, 2018.
Prior Publication US 2022/0318436 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 21/75 (2013.01); G06F 21/56 (2013.01); G06F 21/72 (2013.01); H01L 23/00 (2006.01); H03K 19/173 (2006.01); H04L 9/08 (2006.01); H03K 19/21 (2006.01)
CPC G06F 21/75 (2013.01) [G06F 21/566 (2013.01); G06F 21/72 (2013.01); H01L 23/576 (2013.01); H03K 19/1737 (2013.01); H04L 9/0866 (2013.01); G06F 2221/034 (2013.01); H03K 19/21 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a plurality of physically unclonable function (PUF) cells each configured to generate a cell signal having a unique value;
a combination circuit configured to receive a plurality of signals from the plurality of PUF cells and output a combined signal, wherein the combination circuit is configured to perform a NAND operation;
a first XOR gate configured to receive a low level as a first input and receive the combined signal as a second input, wherein the first XOR gate is configured to output a first digital signal;
a second XOR gate configured to receive a high level as a first input and receive the combined signal as a second input, wherein the second XOR configured gate is to output a second digital signal;
wherein the second digital signal is an inverted signal of the first digital signal.