US 12,189,792 B2
Scalable multi-key memory encryption
Barry E. Huntley, Hillsboro, OR (US); Hormuzd M. Khosravi, Portland, OR (US); Thomas Toll, Portland, OR (US); Ramya Jayaram Masti, Hillsboro, OR (US); Siddhartha Chhabra, Portland, OR (US); and Vincent Von Bokern, Rescue, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 26, 2020, as Appl. No. 17/033,748.
Prior Publication US 2022/0100871 A1, Mar. 31, 2022
Int. Cl. G06F 21/60 (2013.01); G06F 12/06 (2006.01); H04L 9/14 (2006.01)
CPC G06F 21/602 (2013.01) [G06F 12/06 (2013.01); H04L 9/14 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/402 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a core to write data to and read data from a plurality of memory regions, each of the plurality of memory regions to be identified by a corresponding address;
an encryption unit to encrypt data to be written and decrypt data to be read, wherein the encryption unit is to use a plurality of encryption keys;
key identification hardware to use a portion of the corresponding address to look up a corresponding key identifier in a key information data structure, wherein, the corresponding key identifier is one of a plurality of key identifiers, and the corresponding key identifier is to identify one of the plurality of encryption keys to be used to encrypt and decrypt the data; and
an instruction decoder to decode a first instruction to write to the key information data structure, wherein the first instruction is the only way for software to write to the key information data structure and is to write only to the key information structure;
wherein the key information data structure is to include a first indicator corresponding to the corresponding key identifier, the first indicator to indicate whether a memory location identified by the corresponding address is private, the first indicator to be compared to a second indicator provided with the corresponding address for the look up.