US 12,189,777 B2
Secure boot systems and methods for programmable logic devices
Fulong Zhang, Cupertino, CA (US); Srirama Chandra, Portland, OR (US); Sreepada Hegade, San Jose, CA (US); Joel Coplen, Portland, OR (US); Wei Han, Portland, OR (US); and Yu Sun, Shanghai (CN)
Assigned to Lattice Semiconductor Corporation, Hillsboro, OR (US)
Filed by Lattice Semiconductor Corporation, Hillsboro, OR (US)
Filed on Nov. 9, 2020, as Appl. No. 17/093,582.
Application 17/093,582 is a continuation of application No. PCT/US2019/031886, filed on May 10, 2019.
Claims priority of provisional application 62/846,365, filed on May 10, 2019.
Claims priority of provisional application 62/756,001, filed on Nov. 5, 2018.
Claims priority of provisional application 62/756,015, filed on Nov. 5, 2018.
Claims priority of provisional application 62/756,021, filed on Nov. 5, 2018.
Claims priority of provisional application 62/670,487, filed on May 11, 2018.
Prior Publication US 2021/0081536 A1, Mar. 18, 2021
Int. Cl. G06F 9/00 (2018.01); G06F 8/65 (2018.01); G06F 9/445 (2018.01); G06F 11/36 (2006.01); G06F 12/02 (2006.01); G06F 15/177 (2006.01); G06F 21/31 (2013.01); G06F 21/44 (2013.01); G06F 21/57 (2013.01); G06F 21/76 (2013.01); G06F 21/79 (2013.01); G06F 21/85 (2013.01); H03K 19/17768 (2020.01); H04L 9/08 (2006.01); H04L 9/30 (2006.01); H04L 9/32 (2006.01); G06F 21/10 (2013.01)
CPC G06F 21/575 (2013.01) [G06F 8/65 (2013.01); G06F 9/44505 (2013.01); G06F 11/3656 (2013.01); G06F 12/0246 (2013.01); G06F 21/31 (2013.01); G06F 21/44 (2013.01); G06F 21/572 (2013.01); G06F 21/577 (2013.01); G06F 21/76 (2013.01); G06F 21/79 (2013.01); G06F 21/85 (2013.01); H03K 19/17768 (2013.01); H04L 9/0825 (2013.01); H04L 9/085 (2013.01); H04L 9/0877 (2013.01); H04L 9/30 (2013.01); H04L 9/3236 (2013.01); H04L 9/3252 (2013.01); G06F 21/107 (2023.08); H04L 2209/12 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A secure programmable logic device (PLD) secure booting system, comprising:
a secure PLD, wherein the secure PLD comprises a plurality of programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a first configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine, wherein the secure PLD is configured to perform a computer-implemented method comprising:
retrieving a first pre-authentication status associated with the first configuration image from the NVM;
determining the first retrieved pre-authentication status associated with the first configuration image is valid;
booting the PLD fabric of the secure PLD using the first configuration image;
receiving an update configuration image over the configuration I/O or a programmable I/O of the secure PLD;
performing an update pre-authentication process associated with the update configuration image to determine an update pre-authentication status associated with the update configuration image;
selectively storing the update configuration image in the NVM in place of the first configuration image if the update pre-authentication status associated with the update configuration image is valid; and
booting the PLD fabric of the secure PLD using the stored update configuration image without requiring performance of an additional authentication process for the stored update configuration image.