US 12,189,765 B2
Memory system
Joon-Woo Choi, Busan (KR); and Jeong-Tae Hwang, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Nov. 21, 2023, as Appl. No. 18/516,549.
Application 18/516,549 is a division of application No. 16/842,483, filed on Apr. 7, 2020, granted, now 11,861,000.
Claims priority of application No. 10-2019-0096200 (KR), filed on Aug. 7, 2019.
Prior Publication US 2024/0086531 A1, Mar. 14, 2024
Int. Cl. G06F 21/00 (2013.01); G06F 21/55 (2013.01)
CPC G06F 21/554 (2013.01) 4 Claims
OG exemplary drawing
 
1. A memory system comprising:
a first memory and a second memory suitable for sharing a common address,
wherein the first memory includes a first scrambling circuit suitable for generating a first scrambled address by selectively inverting N bits, where N is an integer equal to or greater than 1, of the common address excluding lower N bits in response to the lower N bits of the common address, and
the second memory includes a second scrambling circuit suitable for generating a second scrambled address by selectively inverting the N bits among the remaining bits of the common address excluding the lower N bits in response to the lower N bits of the common address, and
at least one of positions of the N bits that are selectively inverted by the first scrambling circuit and positions of the N bits that are selectively inverted by the second scrambling circuit is different.