US 12,189,726 B2
On-demand paging support for confidential computing
Ravi Sahita, Portland, OR (US); Anjali Singhai Jain, Portland, OR (US); and Reouven Elbaz, Hillsboro, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 30, 2022, as Appl. No. 17/854,670.
Prior Publication US 2022/0335109 A1, Oct. 20, 2022
Int. Cl. G06F 13/28 (2006.01); G06F 9/455 (2018.01); G06F 21/12 (2013.01)
CPC G06F 21/121 (2013.01) [G06F 9/45558 (2013.01); G06F 13/28 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45587 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
circuitry including one or more processors including a first processor, the first processor including a trusted execution environment (TEE) and a plurality of registers, wherein the one or more processors are to:
receive a memory access request associated with a trust domain (TD), one or more direct memory access (DMA) payloads associated with the request being generated by a protocol engine (PE) of a peripheral device and written to a host interface (HIF) of the peripheral device, the HIF including an address translation engine (ATE); and
in response to a page fault being identified for a DMA payload of the one or more DMA payloads:
divert the DMA payload and forward a payload fault to one or more TD fault buffers in a set of registers of the plurality of registers, and
resolve the page fault by an ATE driver and a virtual machine manager (VMM) using the TEE.