CPC G06F 17/16 (2013.01) [G06F 7/4876 (2013.01); G06F 7/501 (2013.01); G06F 7/78 (2013.01); G06N 3/08 (2013.01)] | 20 Claims |
1. A system comprising:
a sparse shard comprising a plurality of multiplier circuits, wherein the sparse shard is configured to:
receive a shard input matrix comprising a number of non-zero values equal to or less than a predetermined maximum non-zero threshold and having a dimension equal to or less than a predetermined dimension threshold, the non-zero threshold corresponding to a number of multiplier circuits of the sparse shard and the dimension threshold corresponding to a maximum matrix input size that the sparse shard can process;
receive a shard input vector comprising a plurality of vector values;
receive, for each of the multiplier circuits, a respective non-zero value of the shard input matrix;
generate, by the plurality of multiplier circuits, one or more products of vector values multiplied with the respective non-zero values of the shard input matrix; and
generate, as output to the sparse shard and using the one or more products, a shard output vector that is the product of applying the shard input vector to the shard input matrix.
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