	US 12,189,571 B2
	Dual pipeline parallel systolic array
Jorge Parra, El Dorado Hills, CA (US); Jiasheng Chen, El Dorado Hills, CA (US); Supratim Pal, Folsom, CA (US); Fangwen Fu, Folsom, CA (US); Sabareesh Ganapathy, Bangalore (IN); Chandra Gurram, Folsom, CA (US); Chunhui Mei, San Diego, CA (US); and Yue Qi, San Diego, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/304,797.
Prior Publication US 2022/0414054 A1, Dec. 29, 2022
Int. Cl. G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)

CPC G06F 15/8046 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/3802 (2013.01); G06F 9/382 (2013.01)]

20 Claims

1. A processing apparatus including:

a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline, and

wherein the systolic array includes a first output memory associated with the first pipeline, a second output memory associated with the second pipeline, and common output circuitry configurable to output from one of the first output memory and the second output memory.