US 12,189,570 B2
Low latency nodes fusion in a reconfigurable data processor
Yun Du, Palo Alto, CA (US); and Jianding Luo, Palo Alto, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on May 19, 2023, as Appl. No. 18/199,572.
Claims priority of provisional application 63/345,762, filed on May 25, 2022.
Prior Publication US 2023/0385231 A1, Nov. 30, 2023
Int. Cl. G06F 8/41 (2018.01); G06F 15/78 (2006.01)
CPC G06F 15/7878 (2013.01) [G06F 8/433 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processing system comprising:
a compiler configured to generate a pipeline of n computational nodes related to a dataflow graph, interleaved between n+1 buffers,
wherein each computational node is coupled to perform calculations based on data received from an immediately preceding buffer of the n+1 buffers and store results of the calculations into an immediately following buffer of the n+1 buffers after a latency,
and wherein the compiler is further configured to remove a buffer of the n+1 buffers from the pipeline based on a comparison of the latencies of the computational nodes.