US 12,189,564 B2
Dynamically-sized data structures on data flow architectures
Abhishek Srivastava, Palo Alto, CA (US); Matthew Vilim, Palo Alto, CA (US); Raghu Prabhakar, San Jose, CA (US); Sankar Rachuru, Palo Alto, CA (US); Zhekun Zhang, Palo Alto, CA (US); Matheen Musaddiq, Palo Alto, CA (US); Apurv Vivek, Palo Alto, CA (US); Sitanshu Gupta, Palo Alto, CA (US); and Ayesha Siddiqua, Palo Alto, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Feb. 14, 2023, as Appl. No. 18/109,590.
Claims priority of provisional application 63/309,908, filed on Feb. 14, 2022.
Prior Publication US 2023/0259477 A1, Aug. 17, 2023
Int. Cl. G06F 13/40 (2006.01)
CPC G06F 13/4059 (2013.01) 18 Claims
OG exemplary drawing
 
1. A data processing system for implementing operations that generate a dynamically-sized output, comprising:
a reconfigurable processor configured to implement:
a first operation that generates an output, wherein a size of the output is unknown during a configuration phase;
a second operation that receives the output of the first operation as an input; and
control circuitry, comprising:
a recording unit that generates control data that is indicative of the size of the output; and
a control unit that fetches the control data from the recording unit and provides the control data to the second operation, wherein the second operation processes the input based on the control data; and
external memory that is coupled to the reconfigurable processor, wherein the control unit stores the control data in the external memory, and wherein the second operation retrieves the control data from the external memory.