US 12,189,555 B2
Low voltage drive circuit for synchronizing transmit data from a host device to channels on a bus
Richard Stuart Seger, Jr., Belton, TX (US); Daniel Keith Van Ostrand, Leander, TX (US); Gerald Dale Morrison, Redmond, WA (US); and Timothy W. Markison, Mesa, AZ (US)
Assigned to SigmaSense, LLC, Austin, TX (US)
Filed by SigmaSense, LLC., Wilmington, DE (US)
Filed on Apr. 26, 2023, as Appl. No. 18/307,710.
Application 18/307,710 is a continuation of application No. 17/647,101, filed on Jan. 5, 2022, granted, now 11,681,641.
Application 17/647,101 is a continuation of application No. 16/670,370, filed on Oct. 31, 2019, granted, now 11,221,980, issued on Jan. 11, 2022.
Prior Publication US 2024/0095203 A1, Mar. 21, 2024
Int. Cl. G06F 13/36 (2006.01)
CPC G06F 13/36 (2013.01) [G06F 2213/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A low voltage drive circuit (LVDC) operable to convey data via a bus, the LVDC comprises:
a digital to analog input circuit operable to convert transmit digital data into combined analog outbound data, wherein the transmit digital data has a data rate based on a host input clock, and wherein a first portion of the combined analog outbound data has a first oscillation rate based on a first transmit channel clock and a second portion of the combined analog outbound data has a second oscillation rate based on a second transmit channel clock;
a drive sense circuit operable to:
convert the combined analog outbound data into an analog transmit signal that is transmitted on the bus;
receive an analog receive signal that is transmitted on the bus; and
convert the analog receive signal into analog inbound data; and
a clock circuit operable to:
generate a transmit input clock to synchronize receiving the transmit digital data from a host associated with the host input clock;
generate the first transmit channel clock based on the host input clock; and
generate the second transmit channel clock based on the host input clock.