US 12,189,549 B2
Variable reference clock signal for data transmission between PHY layer and MAC layer
Geet Govind Modi, Cupertino, CA (US); Sumantra Seth, Bangalore (IN); and Subhashish Mukherjee, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Mar. 27, 2023, as Appl. No. 18/126,602.
Application 18/126,602 is a continuation of application No. 17/390,428, filed on Jul. 30, 2021, granted, now 11,615,040.
Prior Publication US 2023/0229607 A1, Jul. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/20 (2006.01); G06F 1/08 (2006.01)
CPC G06F 13/20 (2013.01) [G06F 1/08 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a physical (PHY) layer and a media access control (MAC) layer, the PHY layer including:
a rate detection circuit configured to determine an adopted clock rate for data transmission between the PHY layer and the MAC layer, and in response, provide a rate detection signal indicative of the adopted clock rate;
a reference clock generator having an input coupled to the rate detection circuit and having a reference clock output, the reference clock generator configured to provide at the reference clock output a reference clock signal that is based on the rate detection signal; and
a PHY interface having a data input, a data output, and a clock input, in which the clock input is coupled to the reference clock output; and
the MAC layer including a MAC interface having a clock input coupled to the reference clock output, a data input coupled to the data output of the PHY interface, and a data output coupled to the data input of the PHY interface.