US 12,189,546 B2
Asynchronous communication protocol compatible with synchronous DDR protocol
Dimin Niu, Sunnyvale, CA (US); Mu-Tien Chang, Santa Clara, CA (US); Hongzhong Zheng, Los Gatos, CA (US); Sun Young Lim, Hwasung (KR); Indong Kim, Hwasung (KR); Jangseok Choi, Campbell, CA (US); and Craig Hanson, Champlin, MN (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD.
Filed on Jul. 25, 2022, as Appl. No. 17/872,987.
Application 17/872,987 is a continuation of application No. 16/777,206, filed on Jan. 30, 2020, granted, now 11,397,698, issued on Jul. 26, 2022.
Application 16/777,206 is a continuation of application No. 15/233,850, filed on Aug. 10, 2016, granted, now 10,621,119, issued on Apr. 14, 2020.
Claims priority of provisional application 62/347,569, filed on Jun. 8, 2016.
Claims priority of provisional application 62/303,349, filed on Mar. 3, 2016.
Prior Publication US 2022/0358060 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/1673 (2013.01) [G06F 13/4068 (2013.01); G06F 13/42 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a non-volatile memory; and
an asynchronous memory interface to interface with a memory controller,
wherein the asynchronous memory interface uses memory channel that is operable for synchronous data communication between the memory controller and the device to send a device feedback indicating a status of the device to the memory controller in response to a data access request received from the memory controller.