| CPC G06F 12/14 (2013.01) [G06F 2212/1052 (2013.01)] | 13 Claims |
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1. A memory device, comprising:
a memory array, comprising a plurality of memory cell rows; and
a control logic circuit, coupled to the memory array, and configured to perform an access on the memory array, wherein the control logic circuit comprises:
a reset circuit, configured to reset a count value corresponding to an accessed memory cell row among the plurality of memory cell rows to a predetermined value in responses to a refresh command;
a counter, configured to count a number of the access performed on the plurality of memory cell rows to generate the count value, and set the count value to a random value when the count value is equal to the predetermined value and when the access is performed;
and
a comparator, configured to compare a threshold value and the count value,
wherein when the count value corresponding to the accessed memory cell row reaches to the threshold value, the control logic circuit arranges memory cell rows nearby the accessed memory cell row into a mitigation operation.
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