US 12,189,535 B2
Tiered memory caching
Vydhyanathan Kalyanasundharam, Santa Clara, CA (US); Ganesh Balakrishnan, Austin, TX (US); Kevin M. Lepak, Austin, TX (US); and Amit P. Apte, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 29, 2022, as Appl. No. 18/091,140.
Prior Publication US 2024/0220415 A1, Jul. 4, 2024
Int. Cl. G06F 12/08 (2016.01); G06F 12/0897 (2016.01)
CPC G06F 12/0897 (2013.01) [G06F 2212/1016 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a physical memory comprising at least two partitions, wherein a first partition of the at least two partitions acts as a cache for a second partition of the at least two partitions; and
a controller configured to:
locate, from a processor storage, a partial tag corresponding to a memory request for a line stored in the second partition;
in response to a partial tag hit for the memory request, locate, from the first partition, a full tag for the line; and
process, based on locating the full tag, the requested line from the first partition according to the memory request.